The invention is directed to a method of depositing copper to form copper structures, particularly copper structures used in semiconductor devices. The invention is also directed to a barrier material and the method of making the same. The barrier material can be used as a barrier layer in integrated circuit structures.
In damascene processing, the interconnect structure or wiring pattern is formed within grooves or other openings formed within a dielectric film. Using known techniques a photoresist material is used to define the wiring pattern. The patterned photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. The etched openings are used to define wiring patterns in the dielectric layer. These wiring patterns can extend from one surface of the dielectric layer to the other surface of the dielectric layer. Alternatively, the wiring patterns can be confined to a single layer, that is, not extend to the opposite surface of the dielectric layer. The wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination thereof. Excess metal can then be removed by chemical mechanical polishing through a process known as planarization.
In the single damascene process, via openings are provided in the dielectric layer and filled with a conducting metal, which is often referred to as metallization, to provide electrical contact between layers of wiring levels. In the dual damascene process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with the conducting metal. The dual damascene process can simplify the manufacturing process by eliminating some internal interfaces. Damascene processing followed by metallization is continued for each layer in the electronic component until the electronic device is completed.
Metals are utilized for a variety of applications in semiconductor chips. One such application includes using metals as interconnect structures. One way of forming interconnect structures is electroplating the conducting metal on to semiconductor structures. Recently, copper has started to replace aluminum in interconnect structures in integrated circuit chips. Replacement of aluminum with copper stems at least in part from the lower electrical resistivity of copper. As a result, utilizing copper has resulted in an improvement in IC chip performance. These advantages are described by Luther et al., Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference, 1993, p. 15; and by Edelstein, Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, 1995, p. 301.
One method that may be utilized to deposit copper for chip interconnect structures is the damascene method. See, U.S. Pat. No. 5,612,254, the entire contents of the disclosure of which are incorporated herein by reference. Typically, copper is electroplated to form the structures, as described by Andricacos et al., IBM J. Res. Develop., 42, 567 (1998). Electroplating and the damascene method provide a lower cost versatile method for making copper interconnects.
Electroplated damascene technology begins with the deposition on a semiconductor wafer and patterning of dielectric material. Next, a barrier material is deposited over an entire surface of the wafer including the dielectric material and any underlying portions of the semiconductor wafer exposed by the patterning. The barrier material serves to isolate the silicon circuitry formed in and on the semiconductor wafer from the copper interconnects.
Barrier layer films are needed between the dielectric material and the conductive material in order to prevent atoms of the conductive material from migrating into and at times through the dielectric material and into other active circuit device structures. Migration of conductive material in the device can cause inter-level or intra-level shorts through the dielectric material. Also, junction leakage may result, and threshold voltage (Vt) levels of the transistors formed within the substrate can shift. In some cases, device functionality can be destroyed.
Migration is a particular concern if copper is used as the interconnect material because copper exhibits relatively high mobility in materials used in semiconductor structures. Yet, in spite of this problem, copper is a favored material for interconnect structures because of its superior conductivity. As a result, if copper is used as an interconnect structures, the copper needs to be confined with a barrier layer.
A barrier material conventionally used in conjunction with copper interconnect structures, is tantalum (Ta) and tantalum nitride (TaN). However, because these barrier materials are more reactive than copper, the formation of contaminating interfacial oxides can result in poor adhesion properties between the deposited copper layer and the barrier material. Due to the presence of the contaminating oxides, these conventional barrier materials usually require the deposition of a Cu seed layer prior to standard Cu electrodeposition in a Cu acid bath.
Other materials that can be used as barrier layer materials in conjunction with copper also exhibit shortcomings. For example, titanium nitride also exhibits poor atomic matching on certain atomic planes along the interface it forms with copper. Also, titanium is generally considered unsuitable for use as a barrier material, because titanium combines with copper to form an inter-metallic compound which lowers the conductivity of the copper film. As a result there is a need for new barrier layer materials that exhibit minimal oxide formation, and improved atomic matching.
Following the deposition of barrier material, a thin conducting layer, generally referred to as a xe2x80x9cseedxe2x80x9d layer is deposited over the barrier material. This seed layer acts to carry the electrical current for the electroplating process. Although the seed layer can include any conducting metal(s) or metal alloy(s), typically, the seed layer contains copper.
Following the deposition of a seed layer, the metal to make up the interconnect structure can be electrodeposited over the entire surface of the wafer, filling the patterns of lines and vias in the dielectric and simultaneously forming an xe2x80x9coverburdenxe2x80x9d on the top of the dielectric. The overburden can be removed by chemical-mechanical polishing. Electroplating in damascene technologies entails making electrical contact to the seed layer, at one, or preferably, a multiplicity of points at the edge of the substrate. In some kinds of plating tools, the contact area is exposed to the plating solution. Exposure of the seed layer to the plating solution can result in etching of the seed layer, because the plating solution can include very corrosive materials. Any etching of the seed layer the plating bath can imperil the contact and as a result the quality of the electroplated metal.
Furthermore, the ability of electroplating processes to fill damascene patterns, particularly dual damascene patterns, which can have increasingly high aspect ratios as the dimensions of VLSI technology shrink and essentially vertical side walls, is critically dependent on the integrity of the seed layer that carries the plating current. Missing seed layer, whether as a result of problems in deposition or etching by the plating solution can lead to a void in the electroplated metal. Voids in the lines substantially increase their resistance and result in poor reliability.
Still another problem associated with the use of a seed layer is the relative differences in the thickness of the seed layer. In general, the thickness of the seed layer is greatest on top of the dielectric than on the side-walls and bottoms of the lines and vias of a damascene pattern, particularly a dual damascene pattern. Although many advances have been made in the physical vapor deposition techniques, which is typically used to deposit the seed layer, coverage of the seed layer on the sides and bottoms of damascene patterns, and particularly dual damascene patterns, is often marginal. Because the thickness of the seed layer can become progressively less toward the bottom of the via, such relatively thin seed layers are more susceptible to being completely removed when attacked by the plating solution.
Marginal seed layers that are barely continuous after deposition can be further thinned by the formation of a native oxide and by dissolution of the oxide in the acidic plating bath before the initiation of plating. As a result, voids can form in lines, and the performance and reliability of the chip can be unsatisfactory.
As a result of the various disadvantages seed layers can impose on the quality of the electrodeposited metal, there is a need to develop new barrier materials that require only a relatively thin seed layer, or no seed layer at all prior to electrodeposition of the conducting metal. Obviously, one advantage of not requiring a seed layer is the streamlining of the chip manufacturing process.
The barrier material of the invention provides for the electrodeposition of copper. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy deposited directly onto the barrier layer in a direct electrodeposition process. The process of the invention includes forming a conducting layer in a semiconductor structure comprising: providing a dielectric layer disposed on an underlayer, providing a barrier layer disposed on the dielectric layer, wherein the barrier layer comprises a dielectric interface surface region, and a copper interface surface with at least 50 atom percent of a copper interface metal; and depositing a conducting layer onto the copper interface surface region of the barrier layer. The conducting layer preferably contains copper or an alloy thereof, and preferably, the conducting layer is deposited by direct electrodeposition.
The process of the invention also includes forming a copper interconnect structure on an electronic device comprising: forming a dielectric layer on an underlayer; forming damascene openings or dual-damascene openings defined by submicron lines in the dielectric layer, wherein the damascene openings or dual-damascene openings have sidewalls and a bottom surface; forming a barrier layer on the sidewalls and the bottom surface, wherein the barrier layer comprises a dielectric interface surface region, and a copper interface surface with at least 50 atom percent of a copper interface metal; depositing a conductor layer containing copper or an alloy thereof by direct electrodeposition; and planarizing the resulting structure to accomplish electrical isolation of interconnect structure.
The invention is also directed to a barrier material. The barrier material is particularly suited for use as a barrier layer in copper interconnect structures found in semiconductor structures. The barrier material of the invention comprises surface regions with one surface region containing at least 50 atom percent of a copper interface metal. The barrier material of the invention can also comprise a gradient concentration of a dielectric interface material and a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof.
The barrier material also contains a surface region containing at least 50 atom percent of a dielectric interface material. The dielectric interface material is selected from tungsten, tungsten nitride, titanium, titanium nitride, tantalum, and tantalum nitride. Other dielectric interface materials can include alloys containing any combination of titanium, tantalum, tungsten, silicon, and nitrogen. In such applications, a surface region of the barrier material proximate to a dielectric contains at least 50 atom percent of a dielectric interface material, and a surface region of the barrier material proximate to a conducting material contains at least 50 atom percent of a copper interface metal.
The semiconductor structure of the invention comprises a dielectric layer disposed on an underlying layer and a barrier layer disposed on the dielectric layer. The barrier layer contains a dielectric interface material and a copper interface metal. The barrier layer can also include a gradient atomic concentration of a copper interface metal with a relatively high atomic concentration of the copper interface metal proximate to a conducting material. The conducting material preferably contains copper or an alloy thereof.